Arrays of P-I-N junctions constructed on silicon wafers enable the implementation of high resolution digital imaging technology. The increasing demand for further improvements to digital imaging applications has resulted in the requirement to provide larger detector arrays containing more picture elements (pixels).
Existing methods for manufacture of visible light detector arrays on silicon wafers generally do not allow for the construction of arrays on wafers less than 125 microns thick. Attempts to produce such arrays have yielded assemblies that are too fragile to handle and are not useful in practical applications. In addition, an optimum bias voltage is in the range of about 30 volts, which is not easily achieved using existing readout circuit techniques.
Prior attempts to solve this problem have included the deposition of conventional PN junctions on complimentary metal oxide semiconductors (CMOS). However, this approach produces an array where each junction has a poor fill factor and a low quantum efficiency. Such problems can occur, among other factors, as a result of recombination effects on the backside of the array after a diamond point turning or some other wafer thinning operation. Additionally, PN junctions are unsuitable for some applications due to their characteristic high capacitance.
Efforts to construct P-I-N junctions on CMOS have been ineffective at least for the reason that the high annealing temperatures required to activate the P-I-N implants destroy the electronic circuitry.
One of the largest visible light imaging arrays currently available is 1.1 square inches on a 3 inch diameter silicon wafer. These arrays typically contain about 1,000 by 1,000 detectors, arranged on 27 micron centers, resulting in one million unit cells. The desire to improve imaging technology requires greater capacity than offered by existing arrays, and necessitates the development of larger arrays. The current three inch wafer size limits the array size.
Another problem experienced with current designs include a difficulty in meeting radiation hardness specifications. A further problem is related to a difficulty in producing fully depleted small unit cells, as it is difficult to deplete the region between the unit cells through thicker semiconductor material when the unit cells have small center-to-center spacings. Another problem relates to array flatness, and hence the ease at which the array can be hybridized with other circuitry, such as a readout integrated circuit (ROIC). In conventional practice one may have to rely on the initial flatness of the wafer, which can be subjected to warping and bowing during fabrication.
It is known to implant the front and back surfaces of a relatively thick Si wafer in order to form an array of P-I-N detectors. However, the resulting structure is thick, and may not meet radiation hardness specifications.